1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly, to a semiconductor integrated circuit containing a logical processing circuit that is operated to process data in accordance with a distributed clock signal from a clock distribution circuit.
2. Description of the Background Art
FIG. 18 is a diagram schematically showing the entire construction of a conventional integrated circuit (LSI) chip (integrated circuit device). In FIG. 18, the LSI chip (semiconductor integrated circuit device) LC includes an analog core circuit AK for processing an analog signal, a digital core circuit DCR for processing a digital signal and an input/output circuit IOK for transmitting and receiving data between the digital core circuit DCR and an external device. Analog core circuit AK includes, for example, a digital/analog conversion circuit and an analog/digital conversion circuit, and externally transmits and receives an analog signal, such as an output signal from a sensor or an image signal.
Digital core circuit DCR includes an internal clock generation circuit CKK for generating an internal clock signal CLKi in accordance with a clock signal CLKe externally supplied, and a digital processing circuit DK for performing a signal processing in a pipeline manner in synchronization with internal clock signal CLKi from internal clock generation circuit CKK. This digital processing circuit DK processes a signal supplied from input/output circuit IOK or analog core circuit AK, and applies the result of processing to the input/output circuit IOK or analog core circuit AK.
Digital processing circuit DK is operated synchronously with internal clock signal CLKi from internal clock generation circuit CKK. In order to operate digital processing circuit DK accurately at high speeds, it is required that internal clock signal CLKi should be transmitted to the respective circuits of digital processing circuit DK at the same phase so that the internal circuits of digital processing circuit DK are operated at the same tiring. In particular, as the scale of the digital processing circuit becomes larger, the interconnection length of the clock signal transfer line becomes longer, and therefore, it is necessary to transmit the internal clock signal to the respective internal circuits without an influence due to a signal propagation delay through the clock signal transfer line.
FIG. 19 is a schematic diagram showing an example of the construction of a conventional digital processing circuit (hereinafter, referred to as a semiconductor integrated circuit). In FIG. 19, the semiconductor integrated circuit (DCR) 1 includes a clock buffer 2 for distributing an internal clock signal supplied to an internal clock node 6 to the various parts of the semiconductor integrated circuit, and a logical circuit group RG for carrying out logical processes in synchronization with the internal clock signal from this clock buffer 2. In FIG. 19, one logical circuit 5, included in the logical circuit group RG, is representatively shown.
Latch circuits 3 and 4, which complementarily enter through and latch states in synchronization with the internal clock signal that is applied through clock nodes 7 and 8 from dock buffer 2, are provided in logical circuit 5. Latch circuit 3 is set to the through state when the internal clock signal applied from clock buffer 2 to clock node 7 goes high, thereby transmitting a signal applied to a data node 9 to logical circuit 5 through a data node 10. Latch circuit 3 is set to the latch state when the internal clock signal on clock node 7 goes low, thereby isolating data nodes 9 and 10 from each other.
Latch circuit 4 is set to the through state when the internal clock signal on clock node 8 goes low, thereby transmitting the logical processing signal applied to data node 11 from logical circuit 5 to data node 12. Latch circuit 4 is set to the latch state when the internal clock signal on clock node 8 goes high, thereby isolating data nodes 11 and 12 from each other.
Clock buffer 2 may be an internal clock generation circuit CKK shown in FIG. 18, or may carry out a buffering on an internal clock signal from internal clock generation circuit CKK for distributing the resultant clock signal to the logical circuit group RG corresponding to digital processing circuit DK.
Semiconductor integrated circuit 1 is constituted by MOS transistors (insulated gate type field effect transistors). The source node of a P-channel MOS transistor of semiconductor integrated circuit 1 is supplied with a power supply voltage Vdd as a one operating power supply voltage from power supply node 17 through a common source node 13. Here, the back gate (substrate area) of the P-channel MOS transistor is supplied with power supply voltage Vdd through a common substrate node 14.
The source of an N-channel MOS transistor that is a component thereof is supplied with a ground voltage (GND; Vss) on a ground node 18 through a common source node 15, and the back gate (substrate area) of this N-channel MOS transistor is also supplied with the ground voltage of ground node 18 through a common substrate node 16.
Semiconductor integrated circuit 1 is operated by using both of power supply voltage Vdd of power supply node 17 and the ground voltage (GND) of ground node 18 as operating power supply voltages. Now, a description will be briefly made of the operation of the circuit device.
The clock signal, applied through clock node 6, is distributed to the each part of semiconductor integrated circuit 1 by clock buffer 2, and applied to each latch (transfer) circuits such as latch circuits 3 and 4 contained in the logical circuit group RG. Clock buffer 2, the structure of which will be described later, carries out a buffering on the clock signal and distributes the resultant clock signal such that the propagation delay of the internal clock signal becomes the same in the respective internal parts of integrated circuit 1.
Latch circuit 3 is set to the through state when the internal clock signal of dock node 7 goes high (logical High level), thereby transmitting the signal on data node 9 to data node 10. Latch circuit 3 also isolates data node 9 from data node 10 when the internal clock signal on clock node 7 goes low (logical Low level). Thus, latch circuit 3 has a function of holding the state immediately before the internal clock signal on clock node 7 changes from the High level to the Low level.
Logical circuit 5 carries out a predetermined logical process on the signal received through latch circuit 3, and outputs a signal representing the result of process to data node 11.
Latch circuit 4 is set to the through state when the internal clock signal, applied from dock buffer 2 to dock node 8, goes low, thereby transmitting the signal applied on the data node 11 to data node 12. Latch circuit 4 is also set to the latch state when the internal clock signal on clock node 8 goes high, thereby electrically separating data node 11 and data node 12.
In other words, when latch circuit 3 is in the through state while latch circuit 4 is in the latch state, logical circuit 5 carries out a logical operation. When the internal dock signals of clock nodes 7 and 8 change to the Low level, latch circuit 3 is set to the latch state to hold data node 10 at the signal state immediately before the change. Thus, there is no change in the logical operation of logical circuit 5, and the result of logical process appearing on data node 11 is transferred to data node 12 on the subsequent stage. The signal of data node 12 serves as an input signal to a logical circuit or other on a subsequent stage.
One pipeline stage is formed by latch circuits 3 and 4, and each stage carries out a logical process in synchronization with the internal clock signal from clock buffer 2. In the logical circuit group RG, signals are successively transferred through the latch circuits in accordance with the internal clock signal so that the so-called pipeline process, in which data is successively transferred in accordance with the internal dock signal, is achieved.
FIG. 20 is a diagram showing an example of the construction of a logical circuit 5 shown in FIG. 19. In FIG. 20, the structure of a CMOS inverter with one input and one output is shown as logical circuit 5. In FIG. 20, logical circuit 5 includes a P-channel MOS transistor 21 and an N-channel MOS transistor 22. P-channel MOS transistor 21 has a source connected to a source node 25, a back gate connected to a substrate node 26, a gate connected to a common node (input node) 23 and a drain connected to a common drain node (output node) 24. N-channel MOS transistor 22 has a gate connected to common gate node 23, a drain connected to common drain node 24, a source connected to a source node 27 and a back gate connected to a substrate node 28.
Source node 25 and substrate node 26 are connected to common source node 13 and common substrate node. 14 shown in FIG. 19, respectively, and power supply voltage Vdd is supplied to the source and the back gate of P-channel MOS transistor 21. Source node 27 and substrate node 28 are coupled to common source node 15 and common substrate node 16 shown in FIG. 19, respectively, and this N-channel MOS transistor 22 receives the ground voltage (Vss) at the source and back gate thereof.
In logical circuit 5 shown in FIG. 20, an input signal IN on common gate node 23 goes low, the source and drain of P-channel MOS transistor 21 are allowed to be coupled, while the source and drain of N-channel MOS transistor 22 are not allowed to be coupled. Therefore, common drain node (output node) 24 is set to the High level at the voltage level determined by the potential of source node 25 by P-channel MOS transistor 21. Source node 25 is connected to power supply node 17 shown in FIG. 19, and therefore, the High level of this output signal OUT is at the level of power supply voltage Vdd.
Referring to FIG. 21, a description will be made of a case in which input signal IN of common gate node 23 changes from the Low level to the High level. It is assumed that the threshold voltage of P-channel MOS transistor 21 is Vthp and that the threshold voltage of N-channel MOS transistor 22 is Vthn. Here, the threshold voltage represents a voltage Vgs applied between the gate and the source when the electrical state between the source and the drain change from the non-conductive state to the conductive state in changing the gate to source voltage in an MOS transistor. The threshold voltage is normally set by adjusting the concentration of impurities in the channel region by adjusting the ion implantation condition in a manufacturing process for forming an MOS transistor, in accordance with conditions such as a power supply voltage.
As represented in FIG. 21, when input signal IN is raised from the Low level so that the voltage between gate 23 and source 27 of N-channel MOS transistor exceeds threshold voltage Vthn, the source and drain of N-channel MOS transistor 22 are allowed to be electrically coupled, thereby starting the voltage of output node 24 to drop.
When the voltage of input node 23 is further raised so that voltage Vgs between gate 23 and source 25 of P-channel MOS transistor 21 becomes smaller than the absolute value of threshold voltage Vthp (higher than the threshold voltage Vthp), P-channel MOS transistor 21 is set to the non-conductive state between the source and drain thereof. Consequently, no charge is supplied to output node 24 from the power supply, and the voltage of output node 24 is set to the Low level at a level determined by the voltage of a source node 27. This source node 27 is connected to ground node 18 in FIG. 19, and the Low level of output signal OUT is set to the level of ground voltage GND. Therefore, when the voltage of input node 23 is at the High level, the voltage of output node 24 is fixed to the ground voltage level.
Next, a description will be given of a case in which the input signal of input node 23 changes from the High level to the Low level. When the voltage on input node 23 lowers from the High level and the voltage Vgs between gate 23 and source 25 of P-channel MOS transistor 21 exceeds threshold voltage Vthp, the source and drain of P-channel MOS transistor 21 are allowed to be electrically coupled to each other, thereby starting the voltage level of output node 24 to rise. The voltage on input node 23 further lowers and the voltage between gate 23 and source 27 of N-channel MOS transistor 22 becomes lower than threshold voltage Vthn, the source and drain of N-channel MOS transistor 22 is set to the electrically non-coupled state. Consequently, at output node 24, no charge is allowed to flow to the ground node, and the voltage of output node 24 is set to the High level at a level determined by the voltage level of source node 25, that is, the level of power supply voltage Vdd.
As shown in FIG. 20, the inverter circuit outputs an inverted signal of input signal IN of input node 23 to output node 24. In general, logical circuit 5 is a circuit with multiple inputs and one output, and receives, in parallel, transfer signals from a plurality of latch circuits 3 depending on its construction. However, the basic construction of logical circuit 5 is a CMOS inverter as shown in FIG. 20, and charging or discharging of an output node is carried out in accordance with the threshold voltage of the MOS transistor of a component and the voltage level of the input signal, to finally determine the voltage level of the output signal.
FIG. 22 is a schematic diagram showing an example of the construction of a clock buffer 2 shown in FIG. 19. In FIG. 22, clock buffer 2 includes a first stage inverter 32a that receives an internal clock signal (or an external clock signal) applied to clock node 6, second stage inverters 32b that are connected in parallel with each other and receive an output signal of first stage inverter 32a, and final stage inverters 32na-32nz that are connected in parallel with each other. Clock signals are transmitted to respective latch circuits of logical circuit group RG through inverters 32a, 32b. . . 32an-32az that are placed in a tree-like shape. This tree-like arrangement of the inverters provides the same propagation delay of the clock signal of the clock distribution paths in dock buffer 2, thereby making it possible to provide the same propagation delay of the clock signals outputted by final stage inverters 32na-32nz. Moreover, inverters 32a-32nz enables a high speed transmission of the clock signal in each dock distribution path.
Internal clock signals from these final stage inverters 32na-32nz are applied, as operation timing signals, to latch groups 33a-33z that are placed in various parts of semiconductor integrated circuit 1 in a distributed manner. Each of inverters 32a, 32b, . . . 32na-32nz has the construction of a CMOS inverter as shown in FIG. 20.
Each of latch groups 33a-33z includes one or more latch circuits. The output signals of the one or more latch circuits are applied to the corresponding logical circuits to carry out a.logical process. Moreover, the output signal of a logical circuit is applied to the one or more latch circuits. The correlation between latch groups 33a-33z and logical circuit groups placed correspondingly is appropriately determined in accordance with the contents of a logical process to be carried out.
FIG. 23 is a diagram showing another construction of clock buffer 2 shown in FIG. 19. In the construction shown in FIG. 23, there is provided a PLL (phase locked loop) circuit 34, for synchronizing and locking the phase of a clock signal applied to clock input node 6 with an internal clock signal applied to a feed back node 35 from final stage inverter 32nz. The output clock signal of PLL circuit 34 is applied to final stage inverter 32a of clock buffer 2. The PLL circuit 34 may be placed corresponding to internal clock generation circuit CKK shown in FIG. 18, or internal clock generation circuit CKK shown in FIG. 18 may include this PLL circuit 34 and clock buffer 2.
In the construction shown in FIG. 23, it is intended to lock the phase of the clock signal applied to clock input node 6 to the internal clock signals applied to respective latch groups 33a-33z. The propagation delay of the clock tree (inverters placed in a tree-like shape) in clock buffer 2 is the same in each signal transmission path. Even when a propagation delay occurs, PLL circuit 34 compensates for the propagation delay and applies a clock signal being in phase with the clock signal applied to clock input node 6 to latch groups 33a-33z. 
FIG. 24 is a diagram showing an example of the construction of latch circuit 3 shown in FIG. 19. In FIG. 24, latch circuit 3 includes an inverter 45 that inverts clock signal CK applied to a clock input node 51 and transmits the resultant signal to a node 57, a CMOS transmission gate CM1 that is rendered conductive in response to the signals on clock input node 51 and internal node 57 and electrically connects a node 52 and a node 53 when made conductive, a CMOS transmission gate CM2 that is rendered conductive complementarily to CMOS transmitter gate CM1 in response to the complementary clock signals on node 51 and node 57, for electrically connecting node 56 and node 53, an inverter 46 that inverts a signal on node 53 and transmits the resultant signal to a node 54, an inverter 47 that inverts the signal on node 54 and transmits the resultant signal to CMOS transmission gate CM2 through node 56, and an inverter 48 that inverts the signal on node 54 and transmits the resultant signal to an output node 55. Output data DO is outputted from output node 55, and transmitted to a corresponding logical circuit.
CMOS transmission gate CM1 includes an N-channel MOS transistor 41 that is rendered conductive, when clock signal CK on clock node 51 is at the High level, to electrically connect node 52 and node 53, and a P-channel MOS transistor 42 that is rendered conductive, when the signal on internal node 57 is at the Low level, to electrically connect node 52 and node 53. A back gate 58 of MOS transistor 41 is connected to common substrate node 16 shown in FIG. 19 and receives a ground voltage. A back gate of MOS transistor 42 is coupled to common substrate node 14 shown in FIG. 19 so as to receive power supply voltage Vdd. These MOS transistors 41 and 42 are set to conductive/non-conductive state in the same phase.
CMOS transmission gate CM2 includes a P-channel MOS transistor 43 that is rendered conductive, when internal dock signal CK on dock node 51 is at the Low level, to electrically connect node 53 and node 56, and an N-channel MOS transistor 44 that is rendered conductive, when the signal w on node 57 is at the High level, to electrically connect node 56 and node 53. A back gate 60 of P-channel MOS transistor 43 is connected to common substrate node 14 shown in FIG. 19 to receive power supply voltage Vdd. A back gate 61 of N-channel MOS transistor 44 is connected to common substrate node 16 shown in FIG. 19 to receive ground voltage GND.
Each of inverters 45-48 has the construction of a CMOS inverter shown in the aforementioned FIG. 20.
When clock signal CK on clock node 51 is at the High level, the voltage of internal node 57 is set to the Low level by inverter 45, making both of MOS transistors 41 and 42 conductive so that data DI applied on node 52 is transmitted to node 53. When clock signal CK is at the Low level, the voltage of node 57 is set to the High level, making both of MOS transistors 41 and 42 non-conductive so that node 52 and node 53 are electrically separated to block the transmission of data DI.
Moreover, as for CMOS transmission gate CM2, when clock signal CK is at the Low level, P-channel MOS transistor 43 and N-channel MOS transistor 44 are rendered conductive to transmit the signal on node 56 to node 53. In the case when clock signal CK is at the High level, since node 57 is set to the Low level so that both MOS transistors 43 and 44 become non-conductive, thereby blocking data transmission from inverter 47 to node 56.
In other word, when clock signal CK is at the High level, transmission gate CM1 is rendered conductive, while transmission gate CM2 is made non-conductive. Thus, data DI, applied through node 52, is transmitted.to internal node 53, and inverted by inverters 46 and 48 so that data having the same logical level as input data DI is outputted from output node 55.
When clock signal CK is at the Low level, CMOS transmission gate CM1 is made non-conductive, while CMOS transmission gate CM2 is made conductive, thereby blocking the transmission of data DI to node 52, while transmitting the output signal of inverter 47 to node 53. Therefore, inverters 46 and 47 have a construction equivalent to a construction of a ring-like connection, to form an inverter latch. Thus, data immediately before clock signal CK falls to the Low level is held on nodes 53 and 54. In other words, the operation of latch circuit 3 shown in the aforementioned FIG. 19 is achieved.
FIG. 25 is a diagram showing an example of the construction of latch circuit 4 shown in FIG. 19. In this construction shown in FIG. 25, the position of inverter 45 is different from that in latch circuit 3 shown in FIG. 24. Specifically, the output signal of inverter 45a for inverting clock signal CK on clock node 51 is supplied to the gates of N-channel MOS transistor 41 and P-channel MOS transistor 43. Clock signal CK is supplied to the gates of MOS transistors 42 and 44. The other arrangement of the circuitry shown in FIG. 25 is the same as that of latch circuit 3 shown in FIG. 24, and therefore, the corresponding parts are indicated by the same reference numerals, and the detailed explanation thereof is omitted.
In the latch circuit having the construction of FIG. 25, the phase of clock signal applied to CMOS transmission gates CM1 and CM2 is inverted relative to that of latch circuit 3 shown in FIG. 24. Therefore, when clock signal CK is at the High level, CMOS transmission gate CM1 is made non-conductive, while CMOS transmission gate CM2 is rendered conductive, and latch circuit 4 is set to the latch state. When clock signal CK is at the Low level, CMOS transmission gate CM1 is rendered conductive, while CMOS transmission gate CM2 is made non-conductive, and latch circuit 4 is set to the through state so that data output signal DO is set to a state corresponding to input data signal DI.
Therefore, latch circuit 4 is set to the through state and to the latch state complementarily to latch circuit 3 shown in FIG. 24, and it is possible to achieve the operation of latch circuit 4 shown in FIG. 19.
In this manner, by forming a single pipeline stage using latch circuits that conduct complementarily with each other, processing and transferring of signal/data are carried out in synchronization with clock signals in respective stages so that it becomes possible to execute a logical process in a pipeline manner. Moreover, by supplying clock signals equal in the phase to latch circuits 3 and 4 through clock buffers as shown in FIG. 22 or 23, it is possible to carry out capturing and transferring of signals at the same timing at the individual stages.
Here, a clock signal, inputted to semiconductor integrated circuit 1, is distributed to latch groups 33a-33z through the clock buffer as shown in FIG. 22 or FIG. 23. The changes in the clock signal to latch groups 33a-33z need to take place at the same time. For this reason, clock buffer 2 is constituted by clock drivers (inverters) that are arranged in a tree-like shape. However, in an actual process, due to differences in the interconnection-length and interconnection load, a slight offset (variation) occurs in the input timing of the clock signal in each of latch groups 33a-33z. This offset in the timing (phase) in the clock signal is so-called clock skew, and due to this clock skew, an offset occurs in operation timing in each of the groups of latch circuits.
Referring to FIG. 26A, a description will be given of the case in which clock signals reach clock input nodes 7 and 8 shown in FIG. 19 at the same phase. In this case, with respect to node 10, latch circuit 3 is set to the through state in response to a rise of the clock signal of clock node 7, the signal of data node 10 changes in response to the signal on the data node 9. At this time, since the clock signal of clock node 8 is at the High level, latch circuit 4 is set to the latch state, and the signal on the data node 12 does not change. The signal on data node 11 changes after a lapse of a propagation delay time Td through the logical processing of logical circuit 5.
However, if the propagation delay time Td is shorter than the High level period of the clock signal on clock node 8, latch circuit 4 is in the latch state, and during the High level of the clock signal, the signal of data node 12 does not change. Next, when the clock signals falls to the Low level at nodes 7 and 8, latch circuit 3 is set to the latch state while latch circuit 4 is set to the through state. Thus, the signal state of node 12 changes in accordance with data signal DO transmitted from logical circuit 5 to node 11 so that data DO is transmitted. Therefore, when the clock signal of clock node 8 falls to the Low level, the result of processing in the logical circuit is accurately transmitted to data node 12.
Now, referring to FIG. 26B, a description will be given of the case in which the clock signal reaches clock node 7 earlier relative to clock node 8 by time xcex4. In the case where this dock skew xcex4 is greater than propagation delay time Td of the signal from data node 10 to data node 11, when the signal on node 11 changes in accordance with the result of processing in the logical circuit, the signal on node 12 can change in accordance with the processing result, since the dock signal on clock node is still at the Low level, and latch circuit 4 is in the through state. In other words, both of latch circuits 3 and 4 are set to the through level so that the data signal of node 11 is transmitted to node 12 immediately. When the latch circuit 4 enters the latch state in response to the High level of the clock signal of clock node 8, a signal that was changed in the previous cycle is outputted. Therefore, data is transmitted to the circuit on the next stage from the latch circuit 4 a half-cycle earlier. In this case, in the next stage circuit, when the input latch circuit is operated complementarily with latch circuit 4, the input latch circuit is set to the through state, and therefore, the circuit on the next stage carries out a process in accordance with data to be supplied in the next cycle, causing an erroneous operation.
Such a data penetrating phenomenon due to a clock skew is generally referred to as xe2x80x9cracingxe2x80x9d. Once a racing occurs, it is not possible to dissolve the racing even if the clock period is changed since this racing is caused by skew xcex4 in the delay time in the dock distribution (the time xcex4 of the dock skew is constant, and the propagation delay time Td is also constant). Moreover, even if the operation speed in the entire semiconductor integrated circuit 1 is changed by changing the level of the power supply voltage, since the operation speeds of the dock buffer, the latch circuit.and the logical circuit are changed in the same manner, the propagation delay times of the dock signal and data are merely changed, without any change in the relative relationship between skew xcex4 of the clock signal and signal propagation delay Td, and therefore, it is not possible to solve the problem of racing due to the clock skew.
Therefore, once a racing occurs, it causes a failure that cannot be controlled externally. In order to prevent the occurrence of such a xe2x80x9cracingxe2x80x9d, a conventional method inserts a delay circuit having a delay time of not less than clock skew xcex4 to each of logical circuits 5 within the semiconductor integrated circuit. In this case, the sum of the propagation delay time Td and the delay time xcex94 of this delay circuit becomes greater than the dock skew xcex4, thereby making it possible to prevent the occurrence of a racing. However, when the delay time of the delay circuit is made greater so as to provide a sufficient operating margin, a signal propagation delay time in one stage (between latch circuits 3 and 4 that are complementarily operated) becomes greater, and a high-speed operation could not be achieved and the circuit scale is also increased, resulting in increased production cost.
It is an object of the present invention to provide a semiconductor integrated circuit device that can reliably prevent an erroneous operation due to the clock skew.
Another object of the present invention is to provide a semiconductor circuit device that can control an erroneous operation due to data racing caused by dock skew externally.
A semiconductor integrated circuit in accordance with the first aspect of the present invention includes: dock distribution circuitry that receives a first operating voltage and distributes a clock signal with its operation speed determined by the received first operation voltage and includes insulated gate type transistors receiving the first operation voltage at their respective first conduction nodes; a plurality of latch circuits each for transferring a signal applied thereto in accordance with the clock signal from the clock distribution circuit; and at least one logical circuit that is placed corresponding to the plurality of latch circuits and that carries out a logical process on a signal from a corresponding latch circuit to output a resultant signal.
The logical circuit includes insulated gate type transistors, of the same conductivity type as the transistors of the clock distribution circuitry, receiving a second operation voltage at their respective first conduction nodes and has the operation speed determined by the received second operating voltage.
The first and second operation voltages have their voltage levels settable individually.
A semiconductor integrated circuit in accordance with a second aspect includes: clock distribution circuitry that receives a first operating voltage and distributes a clock signal with its operation speed determined by the received first operation voltage and includes insulated gate type transistors receiving the first operation voltage at their respective back gates; a plurality of latch circuits each for transferring a signal applied thereto in accordance with the clock signal from the clock distribution circuit; and at least one logical circuit that is placed corresponding to the plurality of latch circuits and that carries out a logical process on a signal from a corresponding latch circuit to output a resultant signal.
The logical circuit includes insulated gate type transistors, of the same conductivity type as the transistors of the clock distribution circuitry, receiving a second operation voltage at their respective back gates and has the operation speed determined by the received second operating voltage.
A semiconductor integrated circuit in accordance with a third aspect of the present invention includes: clock distribution circuitry for distributing a clock signal; a plurality of transfer circuits operating in accordance with the clock signals from the clock distribution circuit, each for transferring a signal applied thereto in accordance with the dock signal thus distributed; at least one logical circuit placed corresponding to the plurality of transfer circuits, for carrying out a logical process on a signal from a corresponding transfer circuit to output a resultant signal; and an operation speed adjusting circuit for individually adjusting the operation speeds of the dock distribution circuit and the logical circuit.
A semiconductor integrated circuit in accordance with a fourth aspect of the present invention includes: clock distribution circuitry receiving a first operation voltage and having an operation speed determined in accordance with the first operation voltage, for distributing a clock signal; a plurality of latch circuits for transferring received signals in accordance with clock signals received from the clock distribution circuitry; and at least one logic circuit arranged corresponding to the plurality of latch circuits and receiving a second operation voltage other than the first operation voltage and having an operation speed thereof determined in accordance with the second operation voltage, for carrying a logical process on a signal received from a corresponding latch circuit to output a resultant signal.
The first and second operation voltages are applied to the clock distribution circuitry and the logic circuit separately and dedicatedly.
By individually setting the operation speeds of the clock distribution circuit and the logical circuit in accordance with the first and second operation voltages, an operation for reducing only the clock skew or an operation for increasing only the data signal delay without changing a clock skew can be carried out externally, and it is possible to solve an erroneous operation due to racing by the external operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying diagrams.